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SI9105
Vishay Siliconix
SI9105
1-W High-Voltage Switchmode Regulator
FEATURES
* CCITT Compatible * Current-Mode Control * Low Power Consumption (less than 5 mW) * 10- to 120-V Input Range * 200-V, 250-mA MOSFET * Internal Start-Up Circuit * Current-Mode Control * SHUTDOWN and RESET
DESCRIPTION
The SI9105 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc/dc converter in ISDN terminals up to 3 watts. A 0.5-mA max supply current makes possible the design of a dc/dc converter with 60% efficiency at 25 mW, therefore meeting the recommended performance under the CCITT I.430 specifications. This device may be used with an appropriate transformer to implement isolated flyback power converter topologies to provide single or multiple regulated dc outputs (i.e., 5 V). The SI9105 is available in 16-pin wide-body SOIC, 14-pin plastic DIP, and 20-pin PLCC packages, and is specified over the industrial, D suffix (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
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SI9105
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 V VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V ID (Peak) (300 s pulse, 2% duty cycle) . . . . . . . . . . . . . . . . . . . . . 2 A ID (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Logic Inputs (RESET, SHUTDOWN, OSC IN) . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SOURCE). . . . . . . . . . . . . . .-0.3 V to 7 V HV Pre-Regulator Input Current (continuous). . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 16-Pin Plastic Wide-Body SOIC (W Suffix)c . . . . . . . . . . . . . 900 mW 20-Pin PLCC (N Suffix)d . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 mW Thermal Impedance (JA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167C/W 16-Pin Plastic Wide-Body SOIC. . . . . . . . . . . . . . . . . . . . . . .140C/W 20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/C above 25C c. Derate 7.2 mW/C above 25C d. Derate 11.2 mW/C above 25C
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 V to 120 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 k to 1 M Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye Long Term Stabilitye VR ZOUT ISREF TREF OSC IN = VIN (OSC Disabled), RL = 10 M OSC IN = -VIN OSC IN = - VIN, VREF = -VIN OSC IN = -VIN t = 1000 hrs, TA = 125C Room Room Room Full Room 3.92 15 70 4.00 300 100 0.25 5.00 4.08 45 130 1.0 25.00 V k A mV/C mV
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 820 k , ROSC = 910 k
Tempb
Mind
Typ
c
Max
d
Unit
Oscillator
Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente fMAX fOSC f/f TOSC ROSC = 0 See Note e f/f = f (13.5 V) - f (9.5 V)/f (9.5 V) Room Room Room Full 1 32 3 40 10 200 48 15 500 MHz kHz % ppm/ C
Error Amplifier
Feedback Input Voltage Input BIAS Current Open Loop Voltage Gaine Input Offset Voltage Unity Gain Bandwidthe Dynamic Output Impedance Output Current VFB IFB AVOL VOS BW ZOUT IOUT Source (VFB = 3.4 V) Sink (VFB = 4.5 V) OSC IN = -VIN FB Tied to COMP OSC IN = -VIN (OSC Disabled) OSC IN = -VIN, VFB = 4 V OSC IN = -VIN (OSC Disabled) Room Room Room Room Room Room Room Room 0.05 0.5 60 3.96 4 25 80 15 0.8 1 -1.2 0.08 -0.32 40 4.04 500 V nA dB mV MHz k mA
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SI9105
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter
Power Supply Rejection
Limits
D Suffix -40 to 85C
Symbol
PSRR
DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 820 k , ROSC = 910 k 10 V VCC 13.5 V RL = 100 from DRAIN to VCC VFB = 0 V RL = 100 from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1. IIN = 10 A VCC 10 V Pulse Width 300 s, VCC = 7 V IPRE-REGULATOR = 10 A RL = 100 from DRAIN to VCC See Detailed Description
Tempb
Room
Mind
Typ
c
Max
d
Unit
dB
70
Current Limit
Threshold Voltage Delay to Outpute Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG - VUVLO VSOURC
E
Room Room Room Room Room Room Room Room
0.8
1.0 200
1.2 300
V ns V
td +VIN +IIN ISTART VREG VUVLO VDELTA
120 10 8 7.5 7.0 0.25 15 9.3 8.7 0.5 9.7 9.2
A mA
V
Supply
Supply Current Bias Current SHUTDOWN Delay SHUTDOWN Pulse Width RESET Pulse Width Latching Pulse Width SHUTDOWN and RESET Low Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low ICC IBIAS tSD tSW tRW tLW VIL VIH IIH IIL VIN = 10 V VIN = 0 V See Figure 3. VSOURCE = -VIN, See Figure 2. Room Room Room Room Room Room Room Room Room Room -35 8.0 1 -25 5 A 50 50 25 2.0 V ns 0.35 7.5 50 100 0.5 mA A
MOSFET Switch
Breakdown Voltage Drain-Source On Resistance Drain Off Leakage Current Drain Capacitance Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25C, Cold and Hot = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = 5 pF g. Temperature coefficient of rDS(on) is 0.75% per C, typical.
g
V(BR)DSS rDS(on) IDSS CDS
IDRAIN = 100 A IDRAIN = 100 mA VDRAIN = 100 V
Full Room Room Room
200
220 5 7 10 35
V A pF
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SI9105
Vishay Siliconix
TIMING WAVEFORMS
FIGURE 1.
FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
FIGURE 4.
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SI9105
Vishay Siliconix
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Number Function
SOURCE -VIN VCC OSCOUT OSCIN DISCHARGE VREF SHUTDOWN RESET COMP FB BIAS +VIN DRAIN NC
14-Pin Plastic DIP
4 5 6 7 8 9 10 11 12 13 14 1 2 3
16-Pin SOIC
1 2 4 5 6 7 8 9 10 11 12 13 14 16 3, 15
20-Pin PLCC
7 8 9 10 11 12 14 16 17 18 20 2 3 5 1, 4, 6, 13, 15, 19
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SI9105
Vishay Siliconix
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9105 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.3 V. If VCC is not forced to exceed the 9.3-V threshold, then VCC will be regulated to a nominal value of 9.3 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.7 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the preregulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. BIAS To properly set the bias for the SI9105, a 820-k resistor should be tied from BIAS to -VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 7.5 A. Reference Section The reference section of the SI9105 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9105 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1% of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, whose 1-k dynamic output impedance enables it to be used
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with feedback compensation (unlike transconductance amplifiers). A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics graph of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to a maximum of 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5-V pulse amplitude and 0.5-s pulse width, typical values would be 100 pF in series with 3 k to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and can be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an opencollector driver to the SHUTDOWN pin to provide variable shutdown time. Output Switch The output switch is a 7- , 200-V lateral DMOS transistor. Like discrete MOSFETs, the switch contains an intrinsic bodydrain diode. However, the body contact in the SI9105 is connected internally to -VIN and is independent of the SOURCE. TABLE 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN
H H L L H L L
RESET
H
Output
Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change)
SI9105
Vishay Siliconix
APPLICATIONS
FIGURE 5. CCITT Compatible ISDN Terminal Power Supply
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